Phase control circuit and switching regulator

ABSTRACT

A phase control circuit which can stabilize voltage control when used in a switching regulator, and a switching regulator using such a phase control circuit are provided. A switching circuit for generating a first and a second output signals having opposite polarities based on a clock signal, is provided. A PWM latch circuit, reset by a reset signal, for generating a third and a fourth output signals which have phases controlled with respect to the first and the second output signals respectively by a set signal produced based on a control signal and come to have opposite polarities, is provided. A delay circuit for delaying the rising of each of the first through the fourth output signals before outputting each of the first through the fourth output signals is provided for each output signal. A delay clock pulse width setting circuit for generating a delay pulse based on low level periods of the delayed first and second output signals is provided so as to reset the PWM latch circuit using the delay pulse as the reset signal.

FIELD OF THE INVENTION

[0001] The present invention relates to a phase control circuitappropriately used in a resonant switching regulator, etc. which adoptssoft switching so as to reduce switching loss, and the resonantswitching regulator provided with the phase control circuit.

BACKGROUND OF THE INVENTION

[0002] Conventionally, as for a phase control circuit for a switchingregulator, a structure disclosed in U.S. Pat. No. 5,291,384 (Date ofPatent: Mar. 1, 1994) has been known. A phase control circuit disclosedin the patent is structured so as to control a pulse width modulation(PWM) circuit which controls the phases of output signals A and B andoutput signals C and D, using an output pulse of an oscillation circuit.

[0003]FIG. 6 shows a block diagram of the conventional phase controlcircuit. In FIG. 6, an output of a switching circuit 53 is switched by aclock signal 52 outputted from an oscillator 51.

[0004] Output signals XA 54 and XB 55 of the switching circuit 53 haveopposite polarities, and are inputted to output circuits A 56 and B 57,respectively. Delay circuits 56A and 57A are provided in the outputcircuits A 56 and B 57, respectively, and a delay period of each of thedelay circuits 56A and 57A is set by a delay set AB 58. Each of thedelay circuits 56A and 57A causes a delay in the rising timing of anoutput signal A 59 outputted from the output circuit A 56, and in therising timing of an output signal B 510 outputted from the outputcircuit B 57.

[0005] The output signal XA 54 of the switching circuit 53 is alsoconnected to a first input terminal 512 of an XOR circuit 511. To asecond input terminal 513 of the XOR circuit (exclusive OR) 511, asignal from an output terminal of a PWM latch circuit 514 is provided.

[0006] The XOR circuit 511 outputs output signals XC 515 and XD 516, andthese output signals are inputted to output circuits C 517 and D 518,respectively. The output signals XC 515 and XD 516 have oppositepolarities, in the same way as the foregoing output signals XA 54 and XB55.

[0007] The output circuits C 517 and D 518 include delay circuits 517Aand 518A, respectively, in the same way as the output circuits A 56 andB 57. A delay is caused in the rising timing of an output signal C 520outputted from the output circuit C 517, and in the rising timing of anoutput signal D 521 outputted from the output circuit D 518, by a delayperiod set by a delay set CD 519.

[0008] In an error amplification circuit 522, a first reference voltagesource 524 is connected to a positive input terminal 523, and a monitorsignal voltage 526 is inputted to a negative input terminal 525. Thevoltages at the positive input terminal 523 and at the negative inputterminal 525 are compared and their difference is amplified to form anerror signal 527, which is inputted to two comparators 528 and 538.

[0009] To a positive input terminal 529 of the PWM comparator 528, oneof the comparators, the error signal 527, which is an output signal ofthe error amplification circuit 522, is inputted. To a negative inputterminal 530 of the PWM comparator 528, a ramp wave signal 532 formedaccording to the clock signal 52 is inputted via a level shift circuit531. The PWM comparator 528 compares the foregoing two signals andoutputs a first error detection signal 533.

[0010] The first error detection signal 533 is inputted to a setterminal 534 of the PWM latch circuit 514 as an input signal only whenthe clock signal 52 is in a low level. In such a set input, the polarityof each of the output signals C 520 and D 521 is reversed, compared withthe case where the PWM latch circuit 514 is in a reset state.

[0011] The PWM latch circuit 514, once set, keeps the output low untilbeing reset by the clock signal 52. Besides, in the PWM latch circuit514, while a signal is inputted to a reset terminal 535, no signal isapplied to the set terminal 534, and the output of the PWM latch circuit514 is always in a high level.

[0012] Another comparator 538, to which the error signal 527 as anoutput of the error amplification circuit 522 is inputted, compares avoltage level of the error signal 527 and a voltage level (for example,1V) of a second reference voltage source 536. When the voltage level ofthe error signal 527 is lower than the voltage level of the secondreference voltage source 536, the comparator 538 outputs a second errordetection signal 537 (in a high level).

[0013] The second error detection signal 537 has a function to apply nosignal according to the clock signal 52 to the reset terminal 535 of thePWM latch circuit 514. Hence, when the second error detection signal 537is outputted, if a signal is inputted to the set terminal 534 of the PWMlatch circuit 514 even just once, the output of the PWM latch circuit514 is kept low unless the second error detection signal 537 iscancelled (becomes low).

[0014]FIG. 7 shows a resonant switching regulator which controlsregulator output voltage using the phase control circuit shown in FIG.6. FIG. 8 shows a timing chart of the circuit shown in FIG. 7.

[0015] The output signals A 59, B 510, C 520, and D 521 of the phasecontrol circuit are inputted as control signals for switches A 639, B640, C 641, and D 642, respectively, of the resonant switchingregulator. Here, the switches A 639 and D 642, and the switches B 640and C 641 are paired respectively so as to transmit a current through aprimary 643 and supply power to a secondary 644 of a transformer 650.

[0016] When this phase control circuit is used as a controller for theresonant switching regulator, the first reference voltage source 524 isconnected to the positive input terminal 523 of the error amplificationcircuit 522. To the negative input terminal 525 of the erroramplification circuit 522, the monitor signal voltage 526, formed bydividing the voltage of a regulator output terminal 648 to which poweris supplied from the secondary 644 of the transformer 650, is supplied.

[0017] Here, in order to make the voltages inputted to the both inputterminals of the error amplification circuit 522 equal, the phasecontrol circuit controls the switching phases of the paired switches A639, B 640, C 641, and D 642. Then, the phase control circuit adjustspower supply to the secondary 644 of the transformer 650, so that thevoltage of the regulator output terminal 648 comes to have a desiredvoltage level set by the error amplification circuit 522, and thus afeedback control is applied in a system.

[0018] When the voltage level of the monitor signal voltage 526 is muchlower than the reference voltage of the first reference voltage source524 of the error amplification circuit 522, no high signal is applied tothe set terminal 534 of the PWM latch circuit 514. Therefore, the outputof the PWM latch circuit 514 becomes high. Here, the output signals ofthe paired output circuits have the same polarity, and the switchingphases of the paired switches in the resonant switching regulator become0 degree. Under these conditions, power is supplied to the secondary 644of the transformer 650, except during dead time, which is a delayperiod.

[0019] When the voltage level of the monitor signal voltage 526 is muchhigher than the reference voltage of the first reference voltage source524 of the error amplification circuit 522, the second error detectionsignal 537 is outputted. So no high signal is applied to the resetterminal 535 of the PWM latch circuit 514, and if a signal in a highlevel is inputted to the set terminal 534 even just once during thisperiod, the output of the PWM latch circuit 514 becomes low. Here, theoutput signals of the paired output circuits come to have oppositepolarities, and the switching phases of the paired switches in theresonant switching regulator become 180 degrees. In this situation,power is not supplied to the secondary 644 of the transformer 650.

[0020] When the voltage level of the monitor signal voltage 526 is closeto the voltage level of the reference voltage of the first referencevoltage source 524 of the error amplification circuit 522, according tothe comparison by the PWM comparator 528, a signal is supplied to theset terminal 534 of the PWM latch circuit 514.

[0021] However, the sampling period for performing the phase control inthe resonant switching regulator and the controlling transmission timeof the transformer 650 in accordance with the voltage of the regulatoroutput terminal 648 is only when the clock signal 52 of the oscillator51 is in a low level.

[0022] However, the conventional circuit has the following problems.When the voltage level of the error signal 527 as an output signal ofthe error amplification circuit 522 varies from close to the minimumvoltage of the ramp wave signal 532 formed according to the clock signal52 to the voltage level of the second reference voltage source 536, theperiod in which the phases of the paired switches can vary is describedas follows.

[0023] from 180—(Duty×180) degrees to 180 degrees

[0024] (Duty=clock signal width÷oscillation cycle)

[0025] Here, since there is a period during which the voltage cannot becontrolled (the period when the clock signal 52 is in a high level)although power is supplied to the secondary 644 of the transformer 650,the phase change switches logically, and linearity in phase deviationcannot be obtained. That is, the periods in which the paired outputsignals are simultaneously in a high level switch logically (discretely)in the intervals between when the pulse of the clock signal 52 falls andwhen the pulse rises again. This is because no signal is applied to theset terminal 534 of the PWM latch circuit 514 when the clock signal 52is in a high level.

[0026] In other words, when the conventional circuit is used as acontroller for a resonant switching regulator, in a period during whichan input signal to the set terminal 534 cannot be inputted, the outputof the PWM latch circuit 514 is high, so the input signals of the pairedswitches have the same polarity. As a result, a current is transmittedthrough the primary 643 of the transformer 650, and thus power issupplied to the secondary 644. Here, the switching phases of the pairedswitches become 180—(Duty×180) degrees.

[0027] In the circuit shown in FIG. 7, the ramp wave signal 532 islevel-shifted to 1V and inputted to the PWM comparator 528. In thecomparator 538, which has a function to apply no signal to the resetterminal 535 of the PWM latch circuit 514, the comparison referencevoltage is also set at 1V.

[0028] With this structure, if the minimum voltage of the ramp wavesignal 532 is 0V, when the voltage level of the error signal 527outputted from the error amplification circuit 522 becomes lower thanthe minimum voltage of the ramp wave signal 532, no signal is applied tothe reset terminal 535 of the PWM latch circuit 514. Then, thepolarities of the input signals of the paired switches in the resonantswitching regulator are reversed, and power supply to the secondary 644of the transformer 650 is stopped. Here, the switching phases of thepaired switches become 180 degrees.

[0029] In this manner, since the switching phase jumps from180—(Duty×180) degrees to 180 degrees, linearity in phase deviation(that is, responsiveness) cannot be obtained, requiring time tostabilize the voltage at the regulator output terminal 648.

[0030] To solve such a problem, there is a method to narrow the width ofthe clock signal 52. However, since the oscillation frequency of theclock signal 52 is determined (set) by a load connected to the secondary644 of the transformer 650 in the resonant switching regulator, it isdesirable to set the operation range of the oscillation frequency wideso as to achieve versatility. When this is the case, the width of theclock signal 52 varies in a wide range according to the operation rangeof the oscillation frequency.

[0031] Since the range of phase deviation in which output linearitycannot be obtained is determined by a duty, as long as the oscillationfrequency varies and the width of the clock signal 52 varies accordingto the variation of the oscillation frequency, the phase range inquestion does not vary. However, the time range in which outputlinearity cannot be obtained becomes greater with the decrease of theoscillation frequency.

[0032] As another countermeasure, there is a method to set the delayperiod of an output circuit greater than the width of the clock signal52. During the delay period, all the switches in the resonant switchingregulator do not conduct, which means dead time. Thus, since power isnot supplied originally, there is no need to sample the voltage of theregulator output terminal 648.

[0033] However, since the delay period is provided so as to charge anddischarge parasitic capacitors in the switches by resonance and todecrease switching loss, the delay period cannot be always set greaterthan the width of the clock signal 52 determined by a load.

[0034] There is another problem when the second error detection signal537 is outputted. In this case, since the polarities of the inputsignals of the paired switches in the resonant switching regulator arereversed, a current is not transmitted through the primary 643 of thetransformer 650, and thus power is not supplied to the secondary 644.

[0035] Here, the input signals of the switches which are not originallypaired have the same polarity. If each switch has an identical parasiticcapacitor, the delay in each output circuit is also set identical inmany cases. If the delay period is identical and the second errordetection signal 537 is outputted, the conduction start timings of theswitches which are not originally paired coincide.

[0036] When the paired switches operate in phase, a current flowsthrough the primary 643 of the transformer 650 and the switches are notsubjected to stress so much. However, if the voltage of a regulatorinput terminal 646 is high and the conduction start timings of theswitches which are not originally paired coincide when the transformer650 is not in a transmission state, there is no current-flow path andexcessive voltage is applied across the switches, so the switches aresubjected to substantial stress momentarily. Therefore, the foregoingconventional switching regulator has a problem that the switches areeasily deteriorated over time, failing to ensure stabilized operationfor a long time.

SUMMARY OF THE INVENTION

[0037] It is therefore an object of the present invention to provide aphase control circuit which can stabilize voltage control when used in aswitching regulator, and a switching regulator using such a phasecontrol circuit.

[0038] To achieve the foregoing object, a phase control circuit inaccordance with the present invention is structured so as to include:

[0039] a first pair of output stages for generating a first outputsignal and a second output signal based on a clock signal so that thefirst and the second output signals are pulse signals having oppositepolarities;

[0040] a second pair of output stages, reset by a reset signal, forgenerating a third output signal and a fourth output signal which havephases controlled with respect to the first and the second outputsignals by the first and the second output signals respectively and alsoby a set signal produced based on a control signal, so that the thirdand the fourth output signals are pulse signals having oppositepolarities;

[0041] first delay means for delaying, before output, the rising of thefirst through the fourth output signals; and

[0042] delay pulse means for generating a delay pulse based on low levelperiods of the delayed first and second output signals, and forresetting the second pair of output stages using the delay pulse as thereset signal.

[0043] In the foregoing phase control circuit, it is desirable that adelay period is provided so as to reduce switching loss in a resonantswitching regulator to which the first through the fourth output signalsare connected.

[0044] It is also desirable that the foregoing control signal is amonitor signal in accordance with an output voltage of a resonantswitching regulator to which the first through fourth output signals areconnected.

[0045] According to the foregoing structure, a pulse signal whose pulsewidth is equal to a delay period of the first delay means is used as areset signal for the second pair of output stages. With this structure,the second pair of output stages is reset, for example, in dead time ofthe resonant switching regulator. Therefore, the phase deviations of thethird and the fourth output signals can be controlled from 0 degree to180 degrees with respect to the first and the second signals,respectively, without being influenced by the variation in the frequencyof the clock signal, obtaining linearity, that is, responsiveness.

[0046] Consequently, since linearity in phase deviation, that is,responsiveness, can be obtained in the foregoing structure, when usingthe foregoing structure in, for example, a resonant switching regulator,satisfactory voltage control can be achieved in the resonant switchingregulator.

[0047] It is desirable that the phase control circuit further includesblocking means for blocking an input of a set signal to the second pairof output stages in a reset state, based on the delay pulse.

[0048] According to the foregoing structure, by providing the blockingmeans, a set signal is prevented from being inputted to the second pairof output stages during a reset period. Therefore, the phase deviationsof the third and the fourth output signals with respect to the first andthe second signals can be ensured, respectively, which can furtherstabilize voltage control.

[0049] It is desirable that the phase control circuit further includessecond delay means for further delaying the third and the fourth outputsignals according to a period of a delay pulse.

[0050] According to the foregoing structure, in the case of using theforegoing structure in a resonant switching regulator, when the phasedeviations of the third and the fourth output signals with respect tothe first and the second signals are, for example, about 180 degrees,respectively, the first output signal and the third output signal cometo be in phase.

[0051] Here, the simultaneous turning on of a first switch and a thirdswitch among a first through a fourth switches which are provided in theresonant switching regulator and driven by the first through the fourthoutput signals, respectively, can be avoided by a delay produced by thesecond delay means.

[0052] In this manner, the foregoing structure can prevent excessivevoltage from being applied to the first and the third switches, reducingstress to the switches. Consequently, the life of the switches can beprolonged, and thus, the operation of the resonant switching regulatorcan be stabilized and its operation life can be prolonged.

[0053] It is desirable that the phase control circuit further includescomparison means for detecting a control signal, so as to set all thefirst through the fourth output signals to a low level when the controlsignal becomes higher than a predetermined value.

[0054] According to the foregoing structure, in the case of using theforegoing structure in a resonant switching regulator, when an outputvoltage of the resonant switching regulator exceeds a tolerable valueand the control signal based on the output voltage becomes higher than apredetermined value, the comparison means can stop the operation of theresonant switching regulator. Therefore, the foregoing structure canprevent the resonant switching regulator from getting out of control,and prevent a peripheral device from being damaged by the out-of-controlresonant switching regulator.

[0055] It is desirable that, in the phase control circuit, whencancelling the low level setting for each output signal, the comparisonmeans cancels the low level settings for the first and the second outputsignals, and after a delay period, the comparison means cancels the lowlevel settings for the third and the fourth output signals.

[0056] According to the foregoing structure, in the case of using theforegoing structure in, for example, a resonant switching regulator,when cancelling the low level settings for all the output signals, thelow level settings for the first and the second output signals arecancelled, and after a delay period, the low level settings for thethird and the fourth output signals are cancelled. Therefore, thisstructure can avoid the simultaneous turning on of the switches causinga primary of a transformer of the resonant switching regulator not toconduct.

[0057] Thus, when using the foregoing structure in a resonant switchingregulator, stress applied to the switches in the resonant switchingregulator can be reduced. Consequently, the operation of the resonantswitching regulator can be stabilized and its operation life can beprolonged.

[0058] To achieve the foregoing object, a switching regulator inaccordance with the present invention is structured so as to include:

[0059] a first half bridge circuit including a first switch and a secondswitch, connected in series, which are turned on/off according to ahigh/low signal;

[0060] a second half bridge circuit including a third switch and afourth switch, connected in series, which are turned on/off according toa high/low signal;

[0061] a transformer whose primary is connected to the first and thesecond half bridge circuits;

[0062] a resonant circuit, connected between the first and the secondhalf bridge circuits in series with the primary of the transformer, forsoft switching so as to decrease switching loss;

[0063] a rectifier circuit connected to a secondary of the transformer;

[0064] a control signal generator circuit for generating a controlsignal to feed back and control an output from the rectifier circuit,based on the output; and

[0065] a phase control circuit for controlling the turning on/off of thefirst through the fourth switches,

[0066] the phase control circuit including:

[0067] a first pair of output stages for generating a first outputsignal and a second output signal based on a clock signal so that thefirst and the second output signals are pulse signals having oppositepolarities;

[0068] a second pair of output stages, reset by a reset signal, forgenerating a third output signal and a fourth output signal which havephases controlled with respect to the first and the second outputsignals by the first and the second output signals respectively and alsoby a set signal produced based on a control signal, so that the thirdand the fourth output signals are pulse signals having oppositepolarities;

[0069] first delay means for delaying, before output, the rising of thefirst through the fourth output signals; and

[0070] delay pulse means for generating a delay pulse based on low levelperiods of the delayed first and second output signals, and forresetting the second pair of output stages using the delay pulse as thereset signal, and

[0071] the first through the fourth switches of the switching regulatorbeing respectively connected to the first through the fourth outputsignals of the phase control circuit.

[0072] According to the foregoing structure, by using the foregoingphase control circuit, switching loss of the resonant circuit can bereduced by applying a delay. Besides, the phase deviations in the firstand the second half bridge circuits can be controlled from 0 degree to180 degrees, without being influenced by the variation in the frequencyof the clock signal, obtaining linearity, that is, responsiveness.

[0073] As a result, since linearity in phase deviation of the switches,that is, responsiveness, can be obtained in the foregoing structure,satisfactory voltage control can be achieved for output.

[0074] For a fuller understanding of the nature and advantages of theinvention, reference should be made to the ensuing detailed descriptiontaken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0075]FIG. 1 is a block diagram showing one embodiment of a phasecontrol circuit of the present invention.

[0076]FIG. 2 is a block diagram showing another embodiment of a phasecontrol circuit of the present invention.

[0077]FIG. 3 is a block diagram showing still another embodiment of aphase control circuit of the present invention.

[0078]FIG. 4 is a block diagram showing a resonant switching regulatorusing still another embodiment of a phase control circuit of the presentinvention.

[0079]FIG. 5 is a timing chart of the phase control circuit and theresonant switching regulator of the present invention shown in FIG. 4.

[0080]FIG. 6 is a block diagram showing one embodiment of a conventionalphase control circuit (U.S. Pat. No. 5,291,384).

[0081]FIG. 7 is a block diagram showing one embodiment of a resonantswitching regulator using a conventional phase control circuit.

[0082]FIG. 8 is a timing chart showing the operation of the conventionalresonant switching regulator shown in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0083] Referring to the drawings, the following will describe oneembodiment of the present invention in detail.

First Embodiment

[0084]FIG. 1 shows one embodiment of a phase control circuit of thepresent invention as a first embodiment.

[0085] In FIG. 1, an oscillator 11 outputs a clock signal 12 with anoscillation frequency set by an external instruction input. Theoscillation frequency from the oscillator 11 sometimes becomes unstablewhen the power is turned on, etc.

[0086] To solve the problem, the clock signal 12 is first inputted to acounter (CONT) 13 and counted to reach the number of times enough tomake the oscillation frequency stable. Then, the clock signal 12 isinputted to an input terminal ({overscore (CK)}) of a switching circuit14 provided in the next stage. Examples of the switching circuit 14include a T-type flip flop.

[0087] The switching circuit 14 is switched according to the clocksignal 12, and outputs output signals XA 15 and XB 16. The outputsignals XA 15 and XB 16 have opposite polarities (one signal is in a lowlevel while the other signal is in a high level), and are inputted toinput terminals of output circuits A 17 and B 18, respectively.

[0088] The output circuit A 17 is provided with a delay circuit 17A anda first logic circuit 17B, and the output circuit B 18 is provided witha delay circuit 18A and a first logic circuit 18B. Each of the delaycircuits 17A and 18A has a function to set a delay period which occurswhen an output signal rises, and each of the first logic circuits 17Band 18B has a function to keep an output low until a counter completionsignal 19 of the counter 13 is inputted.

[0089] Output circuits C 110 and D 111 are also provided with similarcircuits and have similar functions as the output circuits A 17 and B18. That is, the output circuit C 110 is provided with a delay circuit110A, a first logic circuit 110B, and a second logic circuit 110C as anadditional circuit. The output circuit D 111 is provided with a delaycircuit 11A, a first logic circuit 111B, and a second logic circuit 111Cas an additional circuit.

[0090] Examples of the first logic circuit include an NOR circuit, andexamples of the second logic circuit include an inverter circuit.

[0091] Output signals XC 112 and XD 113 inputted to the output circuitsC 110 and D 111, respectively, are made up of an output of an XORcircuit 115 to which the output signal XB 16 of the switching circuit 14and an output signal of a PWM latch circuit 114 are inputted.

[0092] Here, the output signals XC 112 and XD 113 have oppositepolarities, in the same way as the output signals XA 15 and XB 16. Whena signal is not inputted to a set terminal of the PWM latch circuit 114,output signals A 116 and D 119 of the output circuits A 17 and D 111,respectively, have the same polarity, and output signals B 117 and C 118of the output circuits B 18 and C 110, respectively, have the samepolarity.

[0093] A delay clock pulse width setting circuit 120 generates a delayclock pulse signal 122 whose pulse width is equal to a delay period setby a delay setting terminal 121 based on the output signals A 116 and B117. The delay clock pulse signal 122 is inputted to a gate of aswitching transistor 125 connected between an OSC terminal 123 and a GND124. Besides, between the OSC terminal 123 and the GND 124, a ramp wavegeneration capacitor 158 is connected.

[0094] When the delay clock pulse signal 122 is in a low level, the rampwave generation capacitor 158 is charged by an OSC constant currentcircuit 155 which generates a constant current determined by an externalresistance and an internal reference voltage. When the delay clock pulsesignal 122 is in a high level, the charged ramp wave generationcapacitor 158 is quickly discharged by the switching transistor 125,forming a ramp wave signal 135.

[0095] In an error amplification circuit 126, a first reference voltagesource 129 is connected to a positive input terminal 127, and a monitorsignal voltage 130 is inputted to a negative input terminal 128. Thevoltages at the positive input terminal 127 and at the negative inputterminal 128 are compared and the difference between them is amplifiedto form an error signal 131, which is inputted to a comparator.

[0096] This comparator is a PWM comparator 132. To a positive inputterminal 133 of the PWM comparator 132, the error signal 131, which isan output of the error amplification circuit 126, is inputted. To anegative input terminal 134 of the PWM comparator 132, the ramp wavesignal 135, formed according to the delay clock pulse signal 122, isinputted via a level shift circuit 139. The PWM comparator 132 comparesthe foregoing two signals and outputs a first error detection signal136.

[0097] The first error detection signal 136 is inputted to a setterminal 137 of the PWM latch circuit 114 as an input signal only whenthe delay clock pulse signal 122 formed by the delay clock pulse widthsetting circuit 120 is in a low level, that is, only when either theoutput signal A 116 or the output signal B 117 is in a high level.

[0098] When the foregoing input signal is inputted to the set terminal137, the polarities of the output signals C 118 and D 119 are reversed,compared with the case where the PWM latch circuit 114 is in a resetstate. The PWM latch circuit 114, once set, keeps the output high untilbeing reset by the delay clock pulse signal 122.

[0099] This structure suppresses the possibility that the monitor signalvoltage 130 inputted to the negative input terminal 128 of the erroramplification circuit 126 may fluctuate (vary substantially) due to thatthe output of the PWM latch circuit 114 becomes high.

[0100] Oscillation of an output signal can be prevented by providing alatch operation in the system. However, while a signal is being inputtedto a reset terminal 138 of the PWM latch circuit 114, that is, duringthe delay period of either the output circuit A 17 or the output circuitB 18, the output of the PWM latch circuit 114 always becomes low.

[0101] In this manner, when used in a resonant switching regulator, forexample, the foregoing structure can solve the problem that linearity inphase deviation of each of the paired output signals A 116 and D 119 andthe paired output signals B 117 and C 118 cannot be obtained.

[0102] That is, in the foregoing structure, when used in a resonantswitching regulator, a delay is applied to each output signal inputtedto a switch of the resonant switching regulator when the output signalrises, so as to achieve soft switching which reduces switching loss.During the delay period, each switch is in a nonconducting state, whichmeans dead time. During the dead time, a current is not transmittedthrough a primary of a transformer, and thus power is hardly supplied toa secondary. Therefore, during this dead time, there is no need tosample an output voltage of the secondary.

[0103] Hence, in the phase control circuit of the present invention, thetiming to reset the PWM latch circuit 114 is completed within a delayperiod, which is the dead time of the resonant switching regulator.Further, set input is prevented during the reset timing.

[0104] Thus, in the foregoing structure, the delay clock pulse widthsetting circuit 120 NORs the output signals A 116 and B 117 to producethe delay clock pulse signal 122. By using the delay clock pulse signal122 as a reset signal for the PWM latch circuit 114 and as a signal forgenerating a ramp wave signal, the delay period, which is the dead timeperiod, is used as a period to reset the PWM latch circuit 114.

[0105] With this structure, in the vicinity of the minimum voltage ofthe ramp wave signal 135, which is in question, since the clock signal12 determined by the oscillation frequency is not used as a reset signalfor the PWM latch circuit 114, the phases of the paired switches can bedeviated from 0 degree to 180 degrees without being limited by the widthof the clock signal 12. As a result, linearity in phase deviation isprevented from being impaired.

Second Embodiment

[0106]FIG. 2 shows another embodiment of a phase control circuit of thepresent invention as a second embodiment. In the second embodiment, themembers having the same structure (function) as those in the firstembodiment will be designated by the same reference numerals and theirdescription will be omitted.

[0107] The error signal 131, which is an output of the erroramplification circuit 126, is inputted to a negative input terminal 233of a phase inversion comparator 240, and a second reference voltagesource 242 is connected to a positive input terminal 241 of the phaseinversion comparator 240. As for the phase inversion comparator 240, acomparator with hysteresis is appropriate for use, considering that itsoutput might fluctuate.

[0108] A second error detection signal 243 outputted from the phaseinversion comparator 240 controls an input signal to the reset terminal138 of the PWM latch circuit 114.

[0109] When the voltage level of the error signal 131 becomes lower thanthe voltage level of the second reference voltage source 242 (that is,when the output voltage of the resonant switching regulator reaches themaximum tolerable output value), the second error detection signal 243performs the following control. That is, even if the delay clock pulsesignal 122 in a high level is inputted, no signal is inputted to thereset terminal 138 of the PWM latch circuit 114 (the output of the PWMlatch circuit 114 is maintained in a low level). If a signal (in a highlevel) is inputted to the set terminal 137 of the PWM latch circuit 114even just once, the output of the PWM latch circuit 114 is kept highuntil the second error detection signal 243 becomes low.

[0110] With this structure, the switching is continued, with thepolarities of the output signals A 116 and D 119 and the polarities ofthe output signals B 117 and C 118 reversed (phase deviation of 180degrees). Thus, when the foregoing phase control circuit is used in aresonant switching regulator, no voltage is supplied to the outputterminal of the resonant switching regulator. That is, it is ensuredthat the output of the resonant switching regulator is prevented fromexceeding the maximum tolerable output value.

[0111] Meanwhile, when the output of the error amplification circuit 126reduces to a certain level as described above, the polarity of theoutput signal D 119 and the polarity of the output signal C 118 arereversed with respect to that of the output signal A 116 and the outputsignal B 117, respectively, so as to prevent excessive output. Here, thedelay circuits 17A, 18A, 110A, and 111A introduce delay periods (delaytime) respectively to the output signals A 116, B 117, C 118, and D 119when the signals rise. However, if the delay periods are all identical,the rising timings of the output signals A 116 and C 118, and the risingtimings of the output signals B 117 and D 119 become identical.

[0112] Hence, the second error detection signal 243 and the delay clockpulse signal 122 are inputted to a NAND circuit (second delay means) 244SO as to generate a second delay clock pulse signal 245. The seconddelay clock pulse signal 245 controls the output signals XC 112 and XD113, which are XOR output signals. That is, while the second delay clockpulse signal 245 is outputted, the signals XC 112 and XD 113 are fixedto a high level, and as a result, the output signals C 118 and D 119 arefixed low.

[0113] With this structure, even if the delay settings in the outputcircuits A 17, B 18, C 110, and D 111 are identical, when the seconderror detection signal 243 becomes low, the rising timing of the outputsignal C 118 and the rising timing of the output signal D 119 aredelayed with respect to that of the output signal A 116 and that of theoutput signal B 117, respectively, by the pulse width of the seconddelay clock pulse signal 245.

[0114] Therefore, in the foregoing structure, by using the second delayclock pulse signal 245, the rising timings of the output signals whichare not originally paired are deviated from each other when they are inphase. Thus, the simultaneous turning on of the switches which are notpaired can be avoided, and stress on the switches, which has been aproblem in a conventional structure, can be reduced.

[0115] With this structure, in a resonant switching regulator using theforegoing phase control circuit, the deterioration of the switches canbe suppressed. As a result, the operation of the resonant switchingregulator can be stabilized, and its operation life can be prolonged.

Third Embodiment

[0116]FIG. 3 shows still another embodiment of a phase control circuitof the present invention as a third embodiment. In the third embodiment,the members having the same structure (function) as those in the firstand the second embodiments will be designated by the same referencenumerals and their description will be omitted.

[0117] The error signal 131, which is an output of the erroramplification circuit 126, is inputted to a negative input terminal 333of an intermittent operation comparator 346, and a third referencevoltage source 348 is connected to a positive input terminal 347 of theintermittent operation comparator 346. As for the intermittent operationcomparator 346, a comparator with hysteresis is appropriate for use,considering that its output might fluctuate.

[0118] The intermittent operation comparator 346 outputs a third errordetection signal 349 when the voltage level of the error signal 131becomes lower than the voltage level of the third reference voltagesource 348, and keeps the voltage levels of the output signals A 116, B117, C 118, and D 119 in a low level.

[0119] With this structure, the resonant switching regulator whichoperates in response to these output signals can be operatedintermittently.

[0120] Further, in order to prevent the rising timings of the outputsignals C 118 and D 119 from coinciding with those of the output signalsA 116 and B 117, respectively, when the third error detection signal 349becomes low, the output circuits A 17 and B 18 are controlled by thethird error detection signal 349 in the first logic circuits 17B and18B, respectively, and the output circuits C 110 and D 111 arecontrolled by the third error detection signal 349 in second logiccircuits 210C and 211C, respectively.

[0121] Thus, even when the third error detection signal 349 becomes low,delays are respectively applied as predetermined when the output signalsC 118 and D 119 rise, and the rising timings of the output signals whichare not paired are deviated from each other when they are in phase.Consequently, stress on the switches, which has been a problem in aconventional structure, can be reduced.

Fourth Embodiment

[0122]FIG. 4 shows still yet another embodiment of a phase controlcircuit of the present invention as a fourth embodiment, and oneembodiment of a switching regulator in accordance with the presentinvention. FIG. 5 shows a timing chart of the circuit shown in FIG. 4.In the present embodiment, the members having the same structure(function) as those in the first through the third embodiments will bedesignated by the same reference numerals and their description will beomitted.

[0123] In the foregoing switching regulator, the output signals A 116, B117, C 118, and D 119 in the foregoing phase control circuit areinputted to switches A 463, B 464, C 465, and D 466, respectively, andthe switching of each switch is controlled so as to control outputvoltage of the switching regulator.

[0124] When the switches A 463 and D 466, or the switches B 464 and C465, are in a conducting state, a current from an input power source istransmitted through a primary 468 of a transformer 472, which makes asecondary 469 of the transformer 472 supply power via a rectifiercircuit 475 to a regulator output terminal 470.

[0125] When controlling the switching timings of the four switches toconvert the voltage of a regulator input terminal 467 to the voltage ofthe regulator output terminal 470, there is a problem, that is,switching loss caused when power is consumed for charging anddischarging a parasitic capacitor in each switch at the time ofswitching.

[0126] To solve the problem, a delay period is set in the conductionstart timing of each switch, and the parasitic capacitor in a switch ischarged and discharged during the delay period by the resonance of theparasitic capacitor in each switch and a coil 473, thus decreasingswitching loss.

[0127] To perform switching using resonance so as to decrease switchingloss is called soft switching, and a regulator which performs softswitching is called a resonant switching regulator. The delay period setby the delay setting terminal 121 is determined based on the frequencyof the resonance for decreasing switching loss. For example, the delayperiod is set to one cycle or a half cycle of the foregoing resonancefrequency.

[0128] The circuit shown in FIG. 4 has a function that a delay periodapplied when a signal rises is set when the polarity of the outputsignal D 119 is reversed with respect to that of the output signal A116, or the polarity of the output signal C 118 is reversed with respectto that of the output signal B 117. By this function, the rising timingof the output signal C 118 and the rising timing of the output signal D119 are delayed with respect to that of the output signal A 116 and thatof the output signal B 117, respectively, by the time set by the delayclock pulse width setting circuit 120.

[0129] By this function, the rising timings of the output signals whichare not paired are deviated from each other, decreasing excessivevoltage generated across the switches, which is caused when thetransformer 472 is not in a transmission state and the voltage of theregulator input terminal 467 is high. As a result, damage to theswitches can be reduced.

[0130] Further, the following functions are also provided to theforegoing phase control circuit and the switching regulator.

[0131] A low voltage detection circuit 451 monitors the voltage of thepower source, and when the voltage of the power source becomes lowerthan a predetermined voltage, the low voltage detection circuit 451outputs a standby signal 450. The standby signal 450 fixes all theoutput signals from the output circuits in a low level and places thephase control circuit in a standby condition, so as to prevent amalfunction of the phase control circuit.

[0132] A current monitor circuit 471 is connected between the switches B464 and D 466 of the resonant switching regulator and a regulator GNDterminal 474, and a current monitor signal 453, which is formed byconverting a current flowing through the current monitor circuit 471 toa voltage, is inputted to a CS (current sense) terminal 452.

[0133] If the voltage level of the current monitor signal 453 inputtedto the CS terminal 452 becomes not less than the voltage level of asetting voltage 455 applied to a VSET2 terminal 454 (that is, when ashort occurs on an input side), a short current prevention circuit 456judges that a current exceeding the tolerable amount is flowing throughthe switching regulator. Then, the short current prevention circuit 456makes all the output signals low, and makes all the switches in theresonant switching regulator in a nonconducting state, so as to recoverfrom the short condition immediately.

[0134] A peak current detection circuit 459 compares the voltage levelof the current monitor signal 453 inputted to the CS terminal 452 andthe voltage level of a setting voltage 458 applied to a VSET1 terminal457, similarly as the short current prevention circuit 456. When thevoltage level of the current monitor signal 453 becomes not less thanthe voltage level of the VSET1 terminal 457, the peak current detectioncircuit 459 inputs a signal to the set terminal 137 of the PWM latchcircuit 114 only when the delay clock pulse signal 122 is not inputted,in the same way as the PWM comparator 132. Thus, the polarities of thepaired output signals are reversed. With this structure, when a shortoccurs on an input side, recovery from the short condition can beimmediately carried out also by the peak current detection circuit 459.

[0135] A soft start circuit 460 gradually increases the amount of thepower supplied for the output voltage of the resonant switchingregulator from 0 when the switching regulator is activated. This is toprevent that, due to the flow of an excessive inrush current generatedin a transformer or a condenser when the switching regulator isactivated, the input voltage varies and influences other loads. In thesoft start circuit 460, a soft start capacitor 461 is connected betweenthe positive input terminal 127 of the error amplification circuit 126and the GND 124, and a soft start resistor 462 is connected between thefirst reference voltage source 129 and the positive input terminal 127.

[0136] When turning on the power source or in a standby condition, ashort occurs between the positive input terminal 127 and the GND 124.When the standby condition is cancelled, the counter 13 operates untilthe output from the oscillator 11 becomes stable, and after the counter13 operates for a predetermined period, the foregoing short condition isalso cancelled. Thus, the voltage applied to the positive input terminal127 gradually increases up to the voltage of the first reference voltagesource 129, according to a time constant determined by the soft startcapacitor 461 and the soft start resistor 462. Accordingly, the phase ofthe output signal also gradually shifts so as to supply power, achievinga soft start.

[0137] A phase control circuit of the present invention may bestructured for controlling a first, a second, a third, and a fourthswitches of a resonant switching regulator by a first, a second, athird, and a fourth output signals, respectively,

[0138] the phase control circuit including:

[0139] a first switching circuit for switching the first and the secondoutput signals;

[0140] a delay circuit for outputting an inverse signal whose rising orfalling is delayed with respect to the first and the second outputsignals, by one cycle or a half cycle of a resonant circuit, so as tocontrol the first switching circuit;

[0141] a second switching circuit for switching the third and the fourthoutput signals; and

[0142] a PWM circuit which provides inversion control on the third andthe fourth output signals with respect to the first and the secondoutput signals, respectively, based on a input signal fed back from theoutput of the switching regulator;

[0143] the switching regulator including:

[0144] a first half bridge circuit in which the first and the secondswitches are connected in series; and

[0145] a second half bridge circuit in which the third and the fourthswitches are connected in series,

[0146] wherein a primary of a transformer and the resonant circuit forsoft switching to reduce switching loss of the first and the second halfbridge circuits are connected in series between the first and the secondhalf bridge circuits, and

[0147] a phase of an inversion output of the second half bridge circuitis controlled with respect to an inversion output of the first halfbridge so as to adjust a current generated at a secondary of thetransformer and to obtain a voltage desired for a smoothing outputvoltage of a rectifier circuit connected to the secondary of thetransformer.

[0148] According to the foregoing structure, by using a pulse signalwhose pulse width is equal to a delay period of the delay circuit as areset signal for the PWM circuit, the PWM circuit is reset in dead timeof the resonant switching regulator. Thus, the phase deviations of thethird and the fourth output signals can be controlled with linearity,from 0 degree to 180 degrees, with respect to the first and the secondsignals, respectively, without being influenced by the variation in theswitching frequency, which permits satisfactory voltage control.

[0149] A phase control circuit of the present invention may be arrangedso as to include:

[0150] an oscillator which supplies a clock signal from an outputterminal;

[0151] a counter circuit which has a first input terminal connected tothe output terminal of the oscillator, a second input terminal to whicha reset signal is inputted, and an output terminal;

[0152] a first logic circuit which has a first input terminal connectedto the output terminal of the oscillator, a second input terminalconnected to the output terminal of the counter circuit, and an outputterminal;

[0153] a switching circuit which has an input terminal connected to theoutput terminal of the first logic circuit, and a first and a secondoutput terminals;

[0154] a first output circuit which has a first input terminal connectedto the first output terminal of the switching circuit, a second inputterminal connected to the output terminal of the counter circuit, and anoutput terminal and a delay control terminal;

[0155] a second output circuit which has a first input terminalconnected to the second output terminal of the switching circuit, asecond input terminal connected to the output terminal of the countercircuit, and an output terminal and a delay control terminal;

[0156] a delay clock pulse width setting circuit which has a first inputterminal connected to the output terminal of the first output circuit, asecond input terminal connected to the output terminal of the secondoutput circuit, and an output terminal;

[0157] a pulse width modulation circuit which has a first input terminalconnected to the output terminal of the delay clock pulse width settingcircuit, and a second input terminal and a first output terminal;

[0158] an error amplification circuit which has a first input terminalto which a monitor signal is inputted, a second input terminal connectedto a reference voltage source, and an output terminal connected to thesecond input terminal of the pulse width modulation circuit;

[0159] a second logic circuit which has a first input terminal connectedto the second output terminal of the switching circuit, a second inputterminal connected to the first output terminal of the pulse widthmodulation circuit, and a first and a second output terminals;

[0160] a third output circuit which has a first input terminal connectedto the first output terminal of the second logic circuit, a second inputterminal connected to the output terminal of the counter circuit, and anoutput terminal and a delay control terminal; and

[0161] a fourth output circuit which has a first input terminalconnected to the second output terminal of the second logic circuit, asecond input terminal connected to the output terminal of the countercircuit, and an output terminal and a delay control terminal.

[0162] The phase control circuit of the present invention may be furtherarranged so as to include a pulse width modulation circuit which has asecond output terminal connected to a third input terminal of the thirdoutput circuit and to a third input terminal of the fourth outputcircuit.

[0163] The phase control circuit of the present invention may be furtherarranged so as to include a pulse width modulation circuit which has asecond output terminal connected to a third input terminal of the firstoutput circuit, to a third input terminal of the second output circuit,to a third input terminal of the third output circuit and to a thirdinput terminal of the fourth output circuit.

[0164] The phase control circuit of the present invention may be furtherarranged so as to include a pulse width modulation circuit which has athird output terminal connected to a third input terminal of the firstoutput circuit, to a third input terminal of the second output circuit,to a fourth input terminal of the third output circuit and to a fourthinput terminal of the fourth output circuit.

[0165] The phase control circuit of the present invention may be furtherarranged so as to include the first, the second, the third, and thefourth output circuits;

[0166] each of the first and the second output circuits being made upof:

[0167] (1) a first time delay circuit which has a first input terminalconnected to the output terminal of the switching circuit, a secondinput terminal connected to the delay control terminal, and an outputterminal, and

[0168] (2) a first output section logic circuit which has a first inputterminal connected to the first input terminal of the first time delaycircuit, a second input terminal connected to the output terminal of thefirst time delay circuit, a third input terminal connected to the outputterminal of the counter circuit, a fourth input terminal connected tothe third output terminal of the pulse width modulation circuit, and anoutput terminal;

[0169] each of the third and the fourth output circuits being made upof:

[0170] (1) a second output section logic circuit which has a first inputterminal connected to the output terminal of the second logic circuit, asecond input terminal connected to the second output terminal of thepulse width modulation circuit, a third input terminal connected to thethird output terminal of the pulse width modulation circuit, and anoutput terminal;

[0171] (2) a second time delay circuit which has a first input terminalconnected to the output terminal of the second output section logiccircuit, a second input terminal connected to the delay controlterminal, and an output terminal; and

[0172] (3) a third output section logic circuit which has a first inputterminal connected to the output terminal of the second output sectionlogic circuit, a second input terminal connected to the output terminalof the second time delay circuit, a third input terminal connected tothe output terminal of the counter circuit, and an output terminal.

[0173] The phase control circuit of the present invention may be furtherarranged so as to include a pulse width modulation circuit whichincludes:

[0174] a level shift circuit which has an input terminal and an outputterminal, and there is a voltage difference between the two terminals;

[0175] a first error voltage detection circuit which has a first inputterminal connected to the output terminal of the error amplificationcircuit, a second input terminal connected to the output terminal of thelevel shift circuit, and an output terminal;

[0176] a second error voltage detection circuit which has a first inputterminal connected to the output terminal of the error amplificationcircuit, a second input terminal connected to a second reference voltagesource, and an output terminal outputting a second error detectionsignal;

[0177] a third logic circuit which has a first input terminal connectedto the output terminal of the second error voltage detection circuit, asecond input terminal connected to the first output terminal of thedelay clock pulse width setting circuit, and an output terminal;

[0178] a fourth logic circuit which has a first input terminal to whicha first error detection signal is inputted from the output terminal ofthe first error detection circuit, a second input terminal connected tothe second output terminal of the delay clock pulse width settingcircuit, and an output terminal;

[0179] a pulse width modulation latch circuit which has a first inputterminal connected to the output terminal of the third logic circuit, asecond input terminal connected to the output terminal of the fourthlogic circuit, and an output terminal connected to the second inputterminal of the second logic circuit; and

[0180] a fifth logic circuit which has a first input terminal connectedto the second output terminal of the delay clock pulse width settingcircuit, a second input terminal connected to the output terminal of thesecond error detection circuit, and an output terminal connected to thesecond input terminal of the second output section logic circuit,

[0181] wherein, by means of the second error detection signal outputtedfrom the second error voltage detection circuit, the polarity of thefourth output signal outputted from the output terminal of the fourthoutput circuit is reversed with respect to that of the first outputsignal outputted from the output terminal of the first output circuit,and the polarity of the third output signal outputted from the outputterminal of the third output circuit is reversed with respect to that ofthe second output signal outputted from the output terminal of thesecond output circuit, and

[0182] even if a delay period of each output circuit is set identical,while the second error detection signal is being outputted from theoutput terminal of the second error voltage detection circuit, therising timing of the third output signal outputted from the outputterminal of the third output circuit is delayed with respect to that ofthe first output signal outputted from the output terminal of the firstoutput circuit, and the rising timing of the fourth output signaloutputted from the output terminal of the fourth output circuit isdelayed with respect to that of the second output signal outputted fromthe output terminal of the second output circuit, by the period of pulsewidth set by the delay clock pulse width setting circuit.

[0183] The phase control circuit of the present invention may be furtherarranged so as to include a third error detection circuit which has afirst input terminal connected to the output terminal of the erroramplification circuit, a second input terminal connected to a thirdreference voltage source, and an output terminal providing a third errorvoltage detection signal; and an intermittent operation circuit which,according to an output voltage level of the error amplification circuit,sets the level of the output signal of each output circuit to a lowlevel, or cancels the low mode setting for the third and the fourthoutput circuits after the delay period so as to prevent the outputsignals of the first and the second output circuits and those of thethird and the fourth output circuits from rising simultaneously at themoment the low mode setting is cancelled, by means of the first outputsection logic circuit which sets the output signals of the first and thesecond output circuits in a low level and the third output section logiccircuit which sets the output signals of the third and the fourth outputcircuits in a low level, both in response to the third error voltagedetection signal.

[0184] A phase control circuit of the present invention may bestructured for controlling a first, a second, a third, and a fourthswitches of a resonant switching regulator by a first, a second, athird, and a fourth output signals, respectively, the resonant switchingregulator including:

[0185] a first half bridge circuit made up of the first and the secondswitches; and

[0186] a second half bridge circuit made up of the third and the fourthswitches,

[0187] wherein a primary of a transformer is connected between the firstand the second half bridge circuits, so that a secondary of thetransformer supplies power when the first and the fourth switches areconducting, or when the second and the third switches are conducting,

[0188] the phase control circuit structured such that:

[0189] the first output signal outputted from an output terminal of afirst output circuit is inputted to the first switch;

[0190] the second output signal outputted from an output terminal of asecond output circuit is inputted to the second switch;

[0191] the third output signal outputted from an output terminal of athird output circuit is inputted to the third switch;

[0192] the fourth output signal outputted from an output terminal of afourth output circuit is inputted to the fourth switch;

[0193] the switching phase of the fourth switch with respect to thefirst switch, and the switching phase of the third switch with respectto the second switch, are varied by varying the polarities of the fourthand the third output signals with respect to the first and the secondoutput signals, respectively, according to a voltage level of a monitorsignal inputted to an input terminal of an error amplification circuit;

[0194] an output voltage outputted by a secondary of a transformer iscontrolled to be a desired voltage;

[0195] when an output voltage of the error amplification circuit reachesa condition to output a second error detection signal according to thevoltage level of the monitor signal, by reversing the polarities of thefourth and the third output signals with respect to the first and thesecond output signals, respectively, the switching phases of the fourthand the third switches are reversed with respect to the first and thesecond switches, respectively;

[0196] a transmission of a current through the primary of thetransformer is stopped; and

[0197] the conduction start timing of the first switch and that of thethird switch, or the conduction start timing of the second switch andthat of the fourth switch, are deviated by a delay clock pulse widthsetting circuit, even when a delay period set for each output circuit isidentical.

[0198] According to the foregoing structure, excessive voltage generatedacross the switches when the transformer is not in a transmission statecan be reduced. Consequently, when using the foregoing structure in aswitching regulator, the operation of the switching regulator can bestabilized, and its operation life can be prolonged.

[0199] The invention being thus described, it will be obvious that thesame may be varied in many ways. Such variations are not to be regardedas a departure from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

What is claimed is:
 1. A phase control circuit comprising: a first pairof output stages for generating a first output signal and a secondoutput signal based on a clock signal so that said first and said secondoutput signals are pulse signals having opposite polarities; a secondpair of output stages, reset by a reset signal, for generating a thirdoutput signal and a fourth output signal which have phases controlledwith respect to the first and the second output signals by the first andthe second output signals respectively and also by a set signal producedbased on a control signal, so that said third and said fourth outputsignals are pulse signals having opposite polarities; first delay meansfor delaying, before output, the rising of the first through the fourthoutput signals; and delay pulse means for generating a delay pulse basedon low level periods of the delayed first and second output signals, andfor resetting said second pair of output stages using said delay pulseas said reset signal.
 2. The phase control circuit of claim 1, wherein:a delay period is provided so as to reduce switching loss in a resonantswitching regulator to which the first through the fourth output signalsare connected.
 3. The phase control circuit of claim 1, wherein: saidcontrol signal is a monitor signal in accordance with an output voltageof a resonant switching regulator to which the first through the fourthoutput signals are connected.
 4. The phase control circuit of claim 2,wherein: said control signal is a monitor signal in accordance with anoutput voltage of a resonant switching regulator to which the firstthrough the fourth output signals are connected.
 5. The phase controlcircuit of claim 1, further comprising blocking means for blocking aninput of a set signal to said second pair of output stages in a resetstate, based on said delay pulse.
 6. The phase control circuit of claim2, further comprising blocking means for blocking an input of a setsignal to said second pair of output stages in a reset state, based onsaid delay pulse.
 7. The phase control circuit of claim 1, furthercomprising second delay means for further delaying the third and thefourth output signals according to a period of said delay pulse.
 8. Thephase control circuit of claim 2, further comprising second delay meansfor further delaying the third and the fourth output signals accordingto a period of said delay pulse.
 9. The phase control circuit of claim1, further comprising comparison means for detecting said controlsignal, so as to set all the first through the fourth output signals toa low level when said control signal becomes higher than a predeterminedvalue.
 10. The phase control circuit of claim 9, wherein: whencancelling a low level setting for each output signal, said comparisonmeans cancels the low level settings for the first and the second outputsignals, and after a delay period, said comparison means cancels the lowlevel settings for the third and the fourth output signals.
 11. Aswitching regulator comprising: a first half bridge circuit including afirst switch and a second switch, connected in series, which are turnedon/off according to a high/low signal; a second half bridge circuitincluding a third switch and a fourth switch, connected in series, whichare turned on/off according to a high/low signal; a transformer whoseprimary is connected to said first and second half bridge circuits; aresonant circuit, connected between said first and second half bridgecircuits in series with the primary of said transformer, for softswitching so as to decrease switching loss; a rectifier circuitconnected to a secondary of said transformer; a control signal generatorcircuit for generating a control signal to feed back and control anoutput from said rectifier circuit, based on said output; and a phasecontrol circuit for controlling the turning on/off of the first throughthe fourth switches, said phase control circuit comprising: a first pairof output stages for generating a first output signal and a secondoutput signal based on a clock signal so that said first and said secondoutput signals are pulse signals having opposite polarities; a secondpair of output stages, reset by a reset signal, for generating a thirdoutput signal and a fourth output signal which have phases controlledwith respect to the first and the second output signals by the first andthe second output signals respectively and also by a set signal producedbased on a control signal, so that said third and said fourth outputsignals are pulse signals having opposite polarities; first delay meansfor delaying, before output, the rising of the first through the fourthoutput signals; and delay pulse means for generating a delay pulse basedon low level periods of the delayed first and second output signals, andfor resetting said second pair of output stages using said delay pulseas said reset signal, and the first through the fourth switches of saidswitching regulator being respectively connected to the first throughthe fourth output signals of said phase control circuit.
 12. Theswitching regulator of claim 11, wherein: a delay period is provided soas to reduce switching loss.
 13. The switching regulator of claim 11,wherein: said control signal is a monitor signal in accordance with anoutput voltage.
 14. The switching regulator of claim 12, wherein: saidcontrol signal is a monitor signal in accordance with an output voltage.15. The switching regulator of claim 11, wherein: said phase controlcircuit further comprises blocking means for blocking an input of a setsignal to said second pair of output stages in a reset state, based onsaid delay pulse.
 16. The switching regulator of claim 12, wherein: saidphase control circuit further comprises blocking means for blocking aninput of a set signal to said second pair of output stages in a resetstate, based on said delay pulse.
 17. The switching regulator of claim11, wherein: said phase control circuit further comprises second delaymeans for further delaying the third and the fourth output signalsaccording to a period of said delay pulse.
 18. The switching regulatorof claim 12, wherein: said phase control circuit further comprisessecond delay means for further delaying the third and the fourth outputsignals according to a period of said delay pulse.
 19. The switchingregulator of claim 11, wherein: said phase control circuit furthercomprises comparison means for detecting a control signal, so as to setall the first through the fourth output signals to a low level when saidcontrol signal becomes higher than a predetermined value.
 20. Theswitching regulator of claim 19, wherein: when cancelling a low levelsetting for each output signal, said comparison means cancels the lowlevel settings for the first and the second output signals, and after adelay period, said comparison means cancels the low level settings forthe third and the fourth output signals.